In semiconductor devices, conductive lines are used to interconnect between various devices or circuitry and or both. For example, power buses are typically made of a metal that is capable of carrying the required current necessary to operate the device.
In a semiconductor memory device, besides metal power buses, the memory array is interconnected by a grid of column (digit or bit) and row (word) lines. The word lines are typically made of polysilicon, topped with a metal silicide, while the bit lines comprise some form of metal.
The bit lines, in a memory array, run basically perpendicular to the word lines and in a parallel fashion to one another. A common characteristic between neighboring bit lines is the capacitive coupling that exists. Digit lines need to be at a specific precharge voltage in order to be read correctly during memory cell sensing. Since there is a capacitive coupling component between neighboring conductors, when a neighboring line is pulled high or low it can couple a digit line above or below the precharge voltage, thus affecting the device's ability to sense data correctly. As memory arrays become denser, the bit lines are crowded even closer together which in turn will increase the capacitive coupling.
It is desirable to reduce the capacitive coupling between conductive lines and in particular between neighboring bits lines of a memory array in order to provide a more efficient array. The present invention discloses a conductive line arrangement that may be used in any semiconductor device that uses substantially parallel conductors, such as in the memory array or a memory device, or the like, that indeed reduces capacitive coupling between neighboring lines (i.e., neighboring bits lines in a memory array).